View AD9601-250EBZ_7616543.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

10-bit, 200 msps/250 msps 1.8 v analog-to-digital converter ad9601 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2007 analog devices, inc. all rights reserved. features snr = 59.4 dbfs @ f in up to 70 mhz @ 250 msps enob of 9.7 @ f in up to 70 mhz @ 250 msps (?1.0 dbfs) sfdr = 81 dbc @ f in up to 70 mhz @ 250 msps (?1.0 dbfs) excellent linearity dnl = 0.2 lsb typical inl = 0.2 lsb typical cmos outputs single data port at up to 250 mhz demultiplexed dual port at up to 2 125 mhz 700 mhz full power analog bandwidth on-chip reference, no external decoupling required integrated input buffer and track-and-hold low power dissipation 274 mw @ 200 msps 322 mw @ 250 msps programmable input voltage range 1.0 v to 1.5 v, 1.25 v nominal 1.8 v analog and digital supply operation selectable output data format (offset binary, twos complement, gray code) clock duty cycle stabilizer integrated data capture clock applications wireless and wired broadband communications cable reverse path communications test equipment radar and satellite subsystems power amplifier linearization functional block diagram agnd pwdn rbias avdd (1.8v) vin+ vin? cml track-and-hold reference adc 10-bit core output staging lvds clk+ clk? clock management serial port reset sclk sdio csb dco? dco+ ovrb ovra dx9 to dx0 drgnd drvdd 10 10 ad9601 07100-001 figure 1. general description the ad9601 is a 10-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. the product operates at up to a 250 msps conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. all necessary func- tions, including a track-and-hold (t/h) and voltage reference, are included on the chip to provide a complete signal conversion solution. the adc requires a 1.8 v analog voltage supply and a differen- tial clock for full performance operation. the digital outputs are cmos compatible and support either twos complement, offset binary format, or gray code. a data clock output is available for proper output data timing. fabricated on an advanced cmos process, the ad9601 is available in a 56-lead lfcsp, specified over the industrial temperature range (?40c to +85c). product highlights 1. high performancemaintains 59.4 dbfs snr @ 250 msps with a 70 mhz input. 2. low powerconsumes only 322 mw @ 250 msps. 3. ease of usecmos output data and output clock signal allow interface to current fpga technology. the on-chip reference and sample-and-hold provide flexibility in system design. use of a single 1.8 v supply simplifies system power supply design. 4. serial port controlstandard serial port interface supports various product functions, such as data formatting, power- down, gain adjust, and output test pattern generation. 5. pin-compatible family12-bit pin-compatible family offered as the ad9626.
ad9601 rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 dc specifications ......................................................................... 3 ac specifications .......................................................................... 4 digital specifications ................................................................... 5 switching specifications .............................................................. 6 timing diagrams .......................................................................... 7 absolute maximum ratings ............................................................ 8 thermal resistance ...................................................................... 8 esd caution .................................................................................. 8 pin configurations and function descriptions ........................... 9 equivalent circuits ......................................................................... 11 typical performance characteristics ........................................... 12 theory of operation ...................................................................... 16 analog input and voltage reference ....................................... 16 clock input considerations ...................................................... 17 power dissipation and power-down mode ........................... 18 digital outputs ........................................................................... 18 timingsingle port mode ....................................................... 19 timinginterleaved mode ....................................................... 19 layout considerations ................................................................... 20 power and ground recommendations ................................... 20 cml ............................................................................................. 20 rbias ........................................................................................... 20 ad9601 configuration using the spi ..................................... 20 hardware interface ..................................................................... 21 configuration without the spi ................................................ 21 memory map .................................................................................. 23 reading the memory map table .............................................. 23 reserved locations .................................................................... 23 default values ............................................................................. 23 logic levels ................................................................................. 23 evaluation board ............................................................................ 25 outline dimensions ....................................................................... 31 ordering guide .......................................................................... 31 revision history 11/07revision 0: initial version
ad9601 rev. 0 | page 3 of 32 specifications dc specifications avdd = 1.8 v, drvdd = 1.8 v, t min = ?40c, t max = +85c, f in = ?1.0 dbfs, full scale = 1.25 v, single port output mode, dcs enabled, unless otherwise noted. table 1. ad9601-200 ad9601-250 parameter 1 temp min typ max min typ max unit resolution 10 10 bits accuracy no missing codes full guaranteed guaranteed offset error 25c 4.0 4.0 mv full ?12 +12 ?12 +12 mv gain error 25c 1.4 1.4 % fs full ?2.1 +4.5 ?2.1 +4.5 % fs differential nonlinearity (dnl) 25c 0.2 0.2 lsb full ?0.5 +0.5 ?0.5 +0.5 lsb integral nonlinearity (inl) 25c 0.2 0.2 lsb full ?0.5 +0.5 ?0.5 +0.5 lsb temperature drift offset error full 8 8 v/c gain error full 0.021 0.021 %/c analog inputs (vin+, vin?) differential input voltage range 2 full 0.98 1.25 1.5 0.98 1.25 1.5 v p-p input common-mode voltage full 1.4 1.4 v input resistance (differential) full 4.3 4.3 k input capacitance 25c 2 2 pf power supply avdd full 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 1.7 1.8 1.9 v supply currents i avdd 3 full 133 142 157 167 ma i drvdd 3 /single port mode 4 full 19 20 22 24 ma i drvdd 3 /interleaved mode 5 full 16 18 ma power dissipation 3 full mw single port mode 4 full 274 291 322 344 mw interleaved mode 5 full 268 315 mw power-down mode supply currents i avdd full 40 40 a i drvdd full 170 170 22 a standby mode supply currents i avdd full 19 19 ma i drvdd full 170 170 22 a 1 see the an-835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions and how these tests were completed. 2 the input range is programmable through the spi, and the range specified reflects the nominal values of each setting. see the memory map section. 3 i avdd and i drvdd are measured with a ?1 dbfs, 10.3 mhz sine input at rated sample rate. 4 single data rate mode; this is the default mode of the ad9601. 5 interleaved mode; user-programmable fe ature. see the memory map section.
ad9601 rev. 0 | page 4 of 32 ac specifications avdd = 1.8 v, drvdd = 1.8 v, t min = ?40c, t max = +85c, f in = ?1.0 dbfs, full scale = 1.25 v, dcs enabled, unless otherwise noted. 1 table 2. ad9601-200 ad9601-250 parameter 2 temp min typ max min typ max unit snr f in = 10 mhz 25c 59.5 59.4 db full 58.5 57.8 db f in = 70 mhz 25c 59.3 59.4 db sinad f in = 10 mhz 25c 59.5 59.4 db full 58.5 57.7 db f in = 70 mhz 25c 59.3 59.4 db effective number of bits (enob) f in = 10 mhz 25c 9.6 9.7 bits f in = 70 mhz 25c 9.6 9.7 bits worst harmonic (second or third) f in = 10 mhz 25c 84 84 dbc full 77 72 dbc f in = 70 mhz 25c 78 81 dbc worst other (sfdr excluding second and third) f in = 10 mhz 25c 88 86 dbc full 80 75 dbc f in = 70 mhz 25c 87 85 dbc two-tone imd 170.2 mhz/171.3 mhz @ ?7 dbfs 25c 81 81 dbfs analog input bandwidth 25c 700 700 mhz 1 all ac specifications tested by driving clk+ and clk? differentially. 2 see the an-835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions and how these tests were completed.
ad9601 rev. 0 | page 5 of 32 digital specifications avdd = 1.8 v, drvdd = 1.8 v, t min = ?40c, t max = +85c, f in = ?1.0 dbfs, full scale = 1.25 v, dcs enabled, unless otherwise noted. table 3. ad9601-200 ad9601-250 parameter 1 temp min typ max min typ max unit clock inputs logic compliance full cmos/lvds/lvpecl cmos/lvds/lvpecl internal common-mode bias full 1.2 1.2 v differential input voltage full 0.2 6 0.2 6 v p-p input voltage range full avdd ? 0.3 avdd + 1.6 avdd ? 0.3 avdd + 1.6 v input common-mode range full 1.1 avdd 1.1 avdd v high level input voltage (v ih ) full 1.2 3.6 1.2 3.6 v low level input voltage (v il ) full 0 0.8 0 0.8 v input resistance (differential) full 16 20 24 16 20 24 k input capacitance full 4 4 pf logic inputs logic 1 voltage full 0.8 vdd 0.8 vdd v logic 0 voltage full 0.2 avdd 0.2 avdd v logic 1 input current (sdio) full 0 0 a logic 0 input current (sdio) full ?60 ?60 a logic 1 input current (sclk, pdwn, csb, reset) full 55 50 a logic 0 input current (sclk, pdwn, csb, reset) full 0 0 a input capacitance 25c 4 4 pf logic outputs high level output voltage full drvdd ? 0.05 drvdd ? 0.05 v low level output voltage full gnd + 0.05 gnd + 0.05 v output coding twos complement, gray code, or offset binary (default) 1 see the an-835 application note, understanding high speed adc testing and evaluation , for a complete set of definitions and how these tests were completed.
ad9601 rev. 0 | page 6 of 32 switching specifications avdd = 1.8 v, drvdd = 1.8 v, t min = ?40c, t max = +85c, f in = ?1.0 dbfs, full scale = 1.25 v, dcs enabled, unless otherwise noted. table 4. ad9601-200 ad9601-250 parameter (conditions) temp min typ max min typ max unit maximum conversion rate full 200 250 msps minimum conversion rate full 40 40 msps clk+ pulse width high (t ch ) full 2.15 2.4 1.8 2.0 ns clk+ pulse width low (t cl ) full 2.15 2.4 1.8 2.0 ns output, single data port mode 1 data propagation delay (t pd ) 25c 3.7 3.7 ns dco propagation delay (t cpd ) 25c 3.4 3.4 ns data to dco skew (t skew ) full 0 0.3 0.55 0 0.3 0.55 ns latency full 6 6 cycles output, interleaved mode 2 data propagation delay (t pda , t pdb ) 25c 3.5 3.5 ns dco propagation delay (t cpda , t cpdb ) 25c 3.0 3.0 ns data to dco skew (t skewa , t skewb ) full 0 0.5 1.1 0 0.5 1.1 ns latency full 6 6 cycles standby recovery 25c 250 250 ns power-down recovery 50 50 s aperture delay (t a ) 25c 0.1 0.1 ns aperture uncertainty (jitter, t j ) 25c 0.2 0.2 ps rms 1 see figure 2. 2 see figure 3.
ad9601 rev. 0 | page 7 of 32 timing diagrams clk+ dco+ n clk? dax n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n ? 7 dco? n + 5 n + 6 n + 7 n + 8 n + 4 n + 3 n + 2 n + 1 t a t pd t skew t cpd t clk = 1/ f clk 07100-042 figure 2. single port mode clk+ dco? n n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n ? 7 clk? dco+ dax dbx n + 1 n + 8 n + 7 n + 6 n + 5 n + 4 n + 3 n + 2 t cpda t skewb t pdb t cpdb t pda t skewa t a t clk = 1/ f clk 07100-043 figure 3. inte rleaved mode
ad9601 rev. 0 | page 8 of 32 absolute maximum ratings table 5. parameter rating electrical avdd to agnd ?0.3 v to +2.0 v drvdd to drgnd ?0.3 v to +2.0 v agnd to drgnd ?0.3 v to +0.3 v avdd to drvdd ?2.0 v to +2.0 v dx0 through dx9 to drgnd ?0.3 v to drvdd + 0.3 v dco+/dco? to drgnd ?0.3 v to drvdd + 0.3 v ovra/ovrb to dgnd ?0.3 v to drvdd + 0.3 v clk+ to agnd ?0.3 v to +3.6 v clk? to agnd ?0.3 v to +3.6 v vin+ to agnd ?0.3 v to avdd + 0.2 v vin? to agnd ?0.3 v to avdd + 0.2 v sdio/dcs to dgnd ?0.3 v to drvdd + 0.3 v pdwn to agnd ?0.3 v to +3.6 v csb to agnd ?0.3 v to +3.6 v sclk/dfs to agnd ?0.3 v to +3.6 v environmental storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering, 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance the exposed paddle must be soldered to the ground plane for the lfcsp package. soldering the exposed paddle to the customer board increases the reliability of the solder joints, maximizing the thermal capability of the package. table 6. package type ja jc unit 56-lead lfcsp (cp-56-2) 30.4 2.9 c/w typical ja and jc are specified for a 4-layer board in still air. airflow increases heat dissipation, effectively reducing ja . in addition, metal in direct contact with the package leads from metal traces, and through holes, ground, and power planes reduces the ja . esd caution
ad9601 rev. 0 | page 9 of 32 pin configurations and function descriptions pin 1 indicator 1 da4 2 da5 3 da6 4 da7 5 da8 6 (msb) da9 7 drvdd 8 drgnd 9 ovra 10 nic 11 nic 12 (lsb) db0 13 db1 14 db2 35 vin+ 36 vin? 37 avdd 38 avdd 39 avdd 40 cml 41 avdd 42 avdd 34 avdd 33 avdd 32 avdd 31 rbias 30 avdd 29 pwdn 1 5 d b 3 1 6 d b 4 1 7 d b 5 1 9 d b 7 2 1 ( m s b ) d b 9 2 0 d b 8 2 2 o v r b 2 3 d r g n d 2 4 d r v d d 2 5 s d i o / d c s 2 6 s c l k / d f s 2 7 c s b 2 8 r e s e t 1 8 d b 6 4 5 c l k ? 4 6 a v d d 4 7 d r v d d 4 8 d r g n d 4 9 d c o ? 5 0 d c o + 5 1 n i c 5 2 n i c 5 3 d a 0 ( l s b ) 5 4 d a 1 4 4 c l k + 4 3 a v d d top view (not to scale) pin 0 (exposed paddle) = agnd ad9601 5 5 d a 2 5 6 d a 3 07100-002 figure 4. pin configuration table 7. single data rate mode pin function descriptions pin o. mnemonic description 30, 32, 33, 34, 37, 38, 39, 41, 42, 43, 46 avdd 1.8 v analog supply. 7, 24, 47 drvdd 1.8 v digital output supply. 0 agnd 1 analog ground. 8, 23, 48 drgnd 1 digital output ground. 35 vin+ analog inputtrue. 36 vin? analog inputcomplement. 40 cml common-mode output pin. enabled through the sp i, this pin provides a reference for the optimized internal bias voltage for vin+/vin?. 44 clk+ clock inputtrue. 45 clk? clock inputcomplement. 31 rbias set pin for chip bias current. (place 1% 10 k resistor terminated to ground.) nominally 0.5 v. 28 reset cmos-compatible chip reset (active low). 25 sdio/dcs serial port interface (spi) data input/output (serial port mode); duty cycle stabilizer select (external pin mode). 26 sclk/dfs serial port interface clock (serial port mode); data format select pin (external pin mode). 27 csb serial port chip select (active low). 29 pwdn chip power-down. 49 dco? data clock outputcomplement. 50 dco+ data clock outputtrue. 53 da0 (lsb) output port a output bit 0 (lsb). 54 da1 output port a output bit 1. 55 da2 output port a output bit 2. 56 da3 output port a output bit 3. 1 da4 output port a output bit 4. 2 da5 output port a output bit 5. 3 da6 output port a output bit 6.
ad9601 rev. 0 | page 10 of 32 pin no. mnemonic description 4 da7 output port a output bit 7. 5 da8 output port a output bit 8. 6 da9 (msb) output port a output bit 9 (msb). 10, 11, 51, 52 nic not internally connected. 9 ovra output port a overrange output bit. 12 db0 (lsb) output port b output bit 0 (lsb). 13 db1 output port b output bit 1. 14 db2 output port b output bit 2. 15 db3 output port b output bit 3. 16 db4 output port b output bit 4. 17 db5 output port b output bit 5. 18 db6 output port b output bit 6. 19 db7 output port b output bit 7. 20 db8 output port b output bit 8. 21 db9 (msb) output port b output bit 9 (msb). 22 ovrb output port b overrange output bit. 1 agnd and drgnd should be tied to a common quiet ground plane.
ad9601 rev. 0 | page 11 of 32 equivalent circuits 1.2v 10k ? 10k ? clk+ clk? avdd 07100-003 figure 5. clock inputs v in+ avdd buf vin? avdd buf 2k? 2k? buf avdd v cml ~1.4v 0 7100-004 figure 6. analog inputs (v cml = ~1.4 v) sclk/dfs reset pdwn 1k ? 30k ? 07100-005 figure 7. equivalent sclk/dfs, reset, pdwn input circuit c sb 1k ? 26k ? avdd 07100-006 figure 8. equivalent csb input circuit 0 7100-044 dr v dd drgnd figure 9. cmos outputs (dx, ovra, ovrb, dco+, dco?) sdio/dcs 1k? drvdd 07100-007 figure 10. equivalent sdio/dcs input circuit
ad9601 rev. 0 | page 12 of 32 typical performance characteristics avdd = 1.8 v, drvdd = 1.8 v, rated sample rate, dcs enabled, t a = 25c, 1.25 v p-p differential input, ain = ?1 dbfs, unless otherwise noted. 0 ?140 0 frequency (mhz) amplitude (dbfs) ?20 ?40 ?60 ?80 ?100 ?120 100 10 20 30 40 50 60 70 80 90 200msps 10.3mhz @ ?1.0dbfs snr: 59.48db enob: 9.58 bits sfdr: 83.79dbc 07100-020 figure 11. ad9601-200 64k point single-tone fft; 200 msps, 10.3 mhz 0 ?140 0 frequency (mhz) amplitude (dbfs) ?20 ?40 ?60 ?80 ?100 ?120 100 10 20 30 40 50 60 70 80 90 200msps 70.3mhz @ ?1.0dbfs snr: 59.3db enob: 9.7 bits sfdr: 78dbc 07100-021 figure 12. ad9601-200 64k point single-tone fft; 200 msps, 70.3 mhz 0 ?140 0 frequency (mhz) amplitude (dbfs) ?20 ?40 ?60 ?80 ?100 ?120 100 10 20 30 40 50 60 70 80 90 200msps 170.3mhz @ ?1.0dbfs snr: 59.35db enob: 9.7 bits sfdr: 83dbc 07100-022 figure 13. ad9601-200 64k point single-tone fft; 200 msps, 170.3 mhz 70k 0 bin number of hits 60k 50k 40k 30k 20k 10k n ? 1 n ? 2 n n + 1 07100-023 figure 14. ad9601-200 grounded input histogram; 200 msps 90 50 0 500 analog input frequency (mhz) snr/sfdr (db) 85 80 75 70 65 60 55 50 100 150 200 250 300 350 400 450 sfdr (+85c) sfdr (+25c) sfdr (?40c) snr (?40c) snr (+25c) snr (+85c) 07100-024 figure 15. ad9601-200 single-tone snr/sfdr vs. input frequency (f in ) and temperature with 1.25 v p-p full scale; 200 msps 0 90 0 amplitude (?dbfs) snr/sfdr (db) 90 80 70 60 50 40 30 20 10 80 70 60 50 40 30 20 10 snr (db) sfdr (dbc) snr (dbfs) sfdr (dbfs) 07100-025 figure 16. ad9601-200 snr/sfdr vs. input amplitude; 170.3 mhz
ad9601 rev. 0 | page 13 of 32 output code inl (lsb) 1.0 ?1.0 01 0 2 4 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 128 256 384 512 640 768 896 07100-026 figure 17. ad9601-200 inl; 200 msps 400 0 5 245 sample rate (msps) current (ma) 350 300 250 200 150 100 50 25 45 65 85 105 125 145 165 185 205 225 total power (mw) i avdd (ma) i dvdd (ma) 07100-027 figure 18. ad9601-200 power supply current vs. sample rate 1.0 ?1.0 01 0 2 4 07100-028 90 50 0 500 analog input frequency (mhz) snr/sfdr (db) output code dnl (lsb) 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 128 256 384 512 640 768 896 figure 19. ad9601-200 dnl; 200 msps 85 80 75 70 65 60 55 sfdr (+25c) sfdr (?40c) sfdr (+85c) snr (+85c) snr (+25c) snr (?40c) 07100-029 50 100 150 200 250 300 350 400 450 figure 20. snr/sfdr vs. analog inpu t frequency, inte rleaved mode vs. temperature 0 ?140 0 frequency (mhz) amplitude (dbfs) ?20 ?40 ?60 ?80 ?100 ?120 20 40 60 80 100 120 250msps 10.3mhz @ ?1.0dbfs snr: 59.4db enob: 9.7 bits sfdr: 84dbc 07100-030 figure 21. ad9601-250 64k point single-tone fft; 250 msps, 10.3 mhz 0 ?140 0 frequency (mhz) amplitude (dbfs) ?20 ?40 ?60 ?80 ?100 ?120 20 40 60 80 100 120 250msps 70.3mhz @ ?1.0dbfs snr: 59.4db enob: 9.7 bits sfdr: 81dbc 07100-031 figure 22. ad9601-250 64k point single-tone fft; 250 msps, 70.3 mhz
ad9601 rev. 0 | page 14 of 32 0 ?140 0 frequency (mhz) amplitude (dbfs) ?20 ?40 ?60 ?80 ?100 ?120 20 40 60 80 100 120 250msps 170.3mhz @ ?1.0dbfs snr: 59.1db enob: 9.60 bits sfdr: 73dbc 07100-032 figure 23. ad9601-250 64k point single-tone fft; 250 msps, 170.3 mhz 70k 0 bin number of hits 60k 50k 40k 30k 20k 10k n ? 2 n ? 1 n n + 1 n + 2 07100-033 figure 24. ad9601-250 grounded input histogram; 250 msps 90 50 0 500 analog input frequency (mhz) snr/sfdr (db) 85 80 75 70 65 60 55 50 100 150 200 250 300 350 400 450 sfdr (+85c) sfdr (+25c) sfdr (?40c) snr (+85c) snr (?40c) snr (+25c) 07100-034 figure 25. ad9601-250 single-tone snr/sfdr vs. input frequency (f in ) and temperature with 1.25 v p-p full scale; 250 msps 100 0 90 0 amplitude (?dbfs) snr/sfdr (db) 90 80 70 60 50 40 30 20 10 80 70 60 50 40 30 20 10 snr (db) sfdr (dbc) snr (dbfs) sfdr (dbfs) 07100-035 figure 26. ad9601-250 snr/sfdr vs. input amplitude; 250 msps, 170.3 mhz 1.0 ?1.0 01 output code inl (lsb) 0 2 4 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 128 256 384 512 640 768 896 07100-036 figure 27. ad9601-250 dnl; 250 msps 400 0 5 245 sample rate (msps) current (ma) 350 300 250 200 150 100 50 25 45 65 85 105 125 145 165 185 205 225 total power (mw) i avdd (ma) i dvdd (ma) 07100-037 figure 28. ad9601 power supply current vs. sample rate
ad9601 rev. 0 | page 15 of 32 1.0 ?1.0 0 output code dnl (lsb) 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 128 256 384 512 640 768 896 07100-038 figure 29. ad9601-250 dnl; 250 msps 90 0 sample rate (msps) snr/sfdr (db) 80 70 60 50 40 30 20 10 sfdr snr 125 75 175 225 275 07100-039 figure 30. snr/sfdr vs. sample rate; ad9626-250 , 170.3 mhz @ ?1 dbfs 2.5 2.0 1.5 1.0 0.5 0 ?0.5 ?60 120100 80 604020 0 ?20?40 gain (%fs) temperature (c) ad9601-210 ad9601-250 ad9601-170 07100-040 figure 31. gain vs. temperature 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 ?40 ?30 ?20 ?10 0 908070605040 302010 offset (mv) temperature (c) ad9601-170 ad9601-210 ad9601-250 07100-041 figure 32. offset vs. temperature
ad9601 rev. 0 | page 16 of 32 theory of operation the ad9601 architecture consists of a front-end sample-and- hold amplifier (sha) followed by a pipelined switched capacitor adc. the quantized outputs from each stage are combined into a final 10-bit result in the digital correction logic. the pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched capacitor dac and interstage residue amplifier (mdac). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the input stage contains a differential sha that can be ac- or dc-coupled. the output-staging block aligns the data, carries out the error correction, and passes the data to the output buffers. the output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. during power- down, the output buffers go into a high impedance state. analog input and voltage reference the analog input to the ad9601 is a differential buffer. for best dynamic performance, the source impedances driving vin+ and vin? should be matched such that common-mode settling errors are symmetrical. the analog input is optimized to provide superior wideband performance and requires that the analog inputs be driven differentially. a wideband transformer, such as mini-circuits? adt1-1wt, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. both analog inputs are self-biased by an on-chip resistor divider to a nominal 1.4 v. an internal differential voltage reference creates positive and negative reference voltages that define the 1.25 v p-p fixed span of the adc core. this internal voltage reference can be adjusted by means of spi control. see the ad9601 configuration using the spi section for more details. differential input configurations optimum performance is achieved while driving the ad9601 in a differential input configuration. for baseband applications, the ad8138 differential driver provides excellent performance and a flexible interface to the adc. the output common-mode voltage of the ad8138 is easily set to avdd/2 + 0.5 v, and the driver can be configured in a sallen-key filter topology to provide band limiting of the input signal. vin+ vin? avdd cml ad8138 523 ? 499 ? 499? 499? 33 ? 33 ? 49.9 ? 1v p-p 0.1f 20pf ad9601 0 7100-008 figure 33. differential input configuration using the ad8138 at input frequencies in the second nyquist zone and above, the performance of most amplifiers may not be adequate to achieve the true performance of the ad9601. this is especially true in if undersampling applications where frequencies in the 70 mhz to 100 mhz range are being sampled. for these applications, differential transformer coupling is the recommended input configuration. the signal characteristics must be considered when selecting a transformer. most rf transformers saturate at frequencies below a few millihertz, and excessive signal power can also cause core saturation, which leads to distortion. in any configuration, the value of the shunt capacitor, c, is dependent on the input frequency and may need to be reduced or removed. vin+ vin? 15? 15? 50? 1.25v p-p 0.1f 2pf ad9601 07100-009 figure 34. differential transformer-coupled configuration as an alternative to using a transformer-coupled input at frequencies in the second nyquist zone, the ad8352 differential driver can be used (see figure 35 ). ad9601 ad8352 0 ? r 0 ? c d r d r g 0.1f 0.1f 0.1f vin+ vin? cml c 0.1f 0.1f 16 1 2 3 4 5 11 r 0.1f 0.1f 10 8, 13 14 v cc 200 ? 200 ? a nalog input a nalog input 07100-010 figure 35. differential input configuration using the ad8352
ad9601 rev. 0 | page 17 of 32 clock input considerations for optimum performance, the ad9601 sample clock inputs (clk+ and clk?) should be clocked with a differential signal. this signal is typically ac-coupled into the clk+ pin and the clk? pin via a transformer or capacitors. these pins are biased internally and require no additional bias. figure 36 shows one preferred method for clocking the ad9601. the low jitter clock source is converted from single-ended to differential using an rf transformer. the back-to-back schottky diodes across the secondary transformer limit clock excursions into the ad9601 to approximately 0.8 v p-p differential. this helps prevent the large voltage swings of the clock from feeding through to other portions of the ad9601 and preserves the fast rise and fall times of the signal, which are critical to low jitter performance. 0.1f 0.1f 0.1f 0.1f clock input 50? 100 ? clk? clk+ adc ad9601 mini-circuits adt1?1wt, 1:1z xfmr schottky diodes: hsm2812 07100-011 figure 36. transformer-coupled differential clock if a low jitter clock is available, another option is to ac couple a differential pecl signal to the sample clock input pins, as shown in figure 37 . the ad9510 / ad9511 / ad9512 / ad9513 / ad9514 / ad9515 family of clock drivers offers excellent jitter performance. 100 ? 0.1f 0.1f 0.1f 0.1f 240 ? 240 ? ad9510/ad9511/ ad9512/ad9513/ ad9514/ad9515 50 ? * 50 ? * clk clk * 50 ? resistors are optional. clk? clk+ adc ad9601 pecl driver clock input clock input 07100-012 figure 37. differential pecl sample clock ad9510/ad9511/ ad9512/ad9513/ ad9514/ad9515 100 ? 0.1f 0.1f 0.1f 0.1f 50 ? * 50 ? * clk clk *50 ? resistors are optional. clk? clk+ adc ad9601 lvds driver clock input clock input 07100-013 figure 38. differential lvds sample clock in some applications, it is acceptable to drive the sample clock inputs with a single-ended cmos signal. in such applications, clk+ should be directly driven from a cmos gate, and the clk? pin should be bypassed to ground with a 0.1 f capacitor in parallel with a 39 k resistor (see figure 39 ). although the clk+ input circuit supply is avdd (1.8 v), this input is designed to withstand input voltages up to 3.3 v, making the selection of the drive logic voltage very flexible. 0.1f 0.1f 0.1f 39k? cmos driver 50? * optional 100? 0.1f clk clk *50 ? resistor is optional. clk? clk+ adc ad9601 a d9510/ad9511/ ad9512/ad9513/ ad9514/ad9515 clock input 07100-014 figure 39. single-ended 1.8 v cmos sample clock 0.1f 0.1f 0.1f cmos driver clk clk * 50 ? resistor is optional. 0.1f clk? clk+ ad9510/ad9511/ ad9512/ad9513/ ad9514/ad9515 adc ad9601 clock input 50 ? * optional 100? 07100-015 figure 40. single-ended 3.3 v cmos sample clock clock duty cycle considerations typical high speed adcs use both clock edges to generate a variety of internal timing signals. as a result, these adcs may be sensitive to the clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic per- formance characteristics. the ad9601 contains a duty cycle stabilizer (dcs) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. this allows a wide range of clock input duty cycles without affecting the performance of the ad9601. when the dcs is on, noise and distortion performance are nearly flat for a wide range of duty cycles. however, some applications may require the dcs function to be off. if so, keep in mind that the dynamic range performance can be affected when operated in this mode. see the ad9601 configuration using the spi section for more details on using this feature. the duty cycle stabilizer uses a delay-locked loop (dll) to create the nonsampling edge. as a result, any changes to the sampling frequency require approximately eight clock cycles to allow the dll to acquire and lock to the new rate.
ad9601 rev. 0 | page 18 of 32 clock jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr for a full-scale input signal at a given input frequency (f a ) due only to aperture jitter (t j ) can be calculated by snr degradation = 20 log 10 [1/2 f a t j ] in this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter specifications. if undersampling applications are particularly sensitive to jitter (see figure 41 ). the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9601. power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. refer to the an-501 application note and the an-756 application note for more in-depth information about jitter performance as it relates to adcs (visit www.analog.com ). 1 10 100 1000 16 bits 14 bits 12 bits 30 40 50 60 70 80 90 100 110 120 130 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps analog input frequency (mhz) 10 bits 8 bits rms clock jitter requirement snr (db) 07100-016 figure 41. ideal snr vs. input frequenc y and jitter for 0 dbfs input signal power dissipation an d power-down mode as shown in figure 28 , the power dissipated by the ad9601 is proportional to its sample rate. the digital power dissipation does not vary much because it is determined primarily by the drvdd supply and bias current of the lvds output drivers. by asserting pdwn (pin 29) high, the ad9601 is placed in standby mode or full power-down mode, as determined by the contents of serial port register 08. reasserting the pdwn pin low returns the ad9601 into its normal operational mode. an additional standby mode is supported by means of varying the clock input. when the clock rate falls below 20 mhz, the ad9601 assumes a standby state. in this case, the biasing network and internal reference remain on, but digital circuitry is powered down. upon reactivating the clock, the ad9601 resumes normal operation after allowing for the pipeline latency. digital outputs digital outputs and timing the off-chip drivers on the ad9601 are cmos-compatible output levels. the outputs are biased from a separate supply (drvdd), allowing isolation from the analog supply and easy interface to external logic. the outputs are cmos devices that swing from ground to drvdd (with no dc load). it is recom- mended to minimize the capacitive load the adc drives by keeping the output traces short (<1 inch, for a total c load < 5 pf). when operating in cmos mode, it is also recommended to place low value (20 ) series damping resistors on the data lines to reduce switching transient effects on performance. the format of the output data is offset binary by default. an example of the output coding format can be found in table 11 . if it is desired to change the output data format to twos comple- ment, see the ad9601 configuration using the spi section. an output clock signal is provided to assist in capturing data from the ad9601. the dco+/dco? signal is used to clock the output data and is equal to the sampling clock (clk) rate in single port mode, and one-half the clock rate in interleaved output mode. see the timing diagrams shown in figure 2 and figure 3 for more information. out-of-range an out-of-range condition exists when the analog input voltage is beyond the input range of the adc. ovra/ovrb is a digital output that is updated along with the data output corresponding to the particular sampled input voltage. thus, ovra/ovrb has the same pipeline latency as the digital data. ovra/ovrb is low when the analog input voltage is within the analog input range and high when the analog input voltage exceeds the input range, as shown in figure 42 . ovra/ovrb remains high until the analog input returns to within the input range and another conversion is completed. by logically and-ing ovra/ovrb with the msb and its complement, overrange high or under- range low conditions can be detected. 1 0 0 0 0 1 o vra/ovrb data outputs ovra/ ovrb +fs ? 1 lsb +fs ? 1/2 lsb +fs ?fs ?fs + 1/2 lsb ?fs ? 1/2 lsb 1111 1111 1111 0000 0000 0000 1111 1111 1111 0000 0000 0000 1111 1111 1110 0001 0000 0000 07100-017 figure 42. ovra/ovrb relation to input voltage and output data
ad9601 rev. 0 | page 19 of 32 timingsingle port mode in single port mode, the cmos output data is available from data port a (da0 to da9). the outputs for port b (db0 to db9) are unused, and are high impedance in this mode. the port a outputs and the differential output data clock (dco+/dco?) switch nearly simultaneously during the rising edge of dco+. in this mode, it is recommended to use the rising edge of dco? to capture the data from port a. the setup and hold time depends on the input sample clock period, and is approximately 1/f clk t skew . timinginterleaved mode in interleaved mode, the output data of the ad9601 is de- multiplexed onto two data port buses, port a (da0 to da9) and port b (db0 to db9). the output data and differential data capture clock switch at one-half the rate of the sample clock input (clk+/clk?), increasing the setup and hold time for the external data capture circuit relative to single port mode (see figure 3 , interleaved mode timing diagram). the two ports switch on alternating sample clock cycles, with the data for port a being valid during the rising edge of dco+, and the data for port b being valid during the rising edge of dco?. the pipeline latency for both ports is six sample clock cycles. due to the random nature of the 2 circuit that generates the timing for the output stage in interleaved mode, the first data sample during power-up can be assigned to either data port a or port b. the user cannot control the polarity of the output data clock relative to the input sample clock. in this mode, it is recom- mended to use the rising edge of dco+ to capture the data from port a, and the rising edge of dco? to capture the data from port b. in both cases, the setup and hold time depends on the input sample clock period, and both are approximately 2/f s t skew . f s /2 spurious because the ad9601 output data rate is at one-half the sampling frequency in interleaved output mode, there is significant f s /2 energy in the outputs of the part, and there is significant energy in the adc output spectrum at f s /2. care must be taken to be certain that this f s /2 energy does not couple into either the clock circuit or the analog inputs of the ad9601. when f s /2 energy is coupled in this fashion, it appears as a spurious tone reflected around f s /4, 3f s /4, 5f s /4, and so on. for example, in a 125 msps sampling application with a 90 mhz single-tone analog input, this energy generates a tone at 97.5 mhz. [(3 125 msps/4 ? 90 mhz) + 3 125 msps/4] depending on the relationship of the if frequency to the center of the nyquist zone, this spurious tone may or may not be in the users band of interest. some residual f s /2 energy is present in the ad9601, and the level of this spur is typically below the level of the harmonics at clock rates. figure 20 shows a plot of the f s /2 spur level vs. the analog input frequency for the ad9601-250. for the specifications provided in table 2 , the f s /2 spur effect is not a factor, as the device is specified in single port output mode.
ad9601 rev. 0 | page 20 of 32 layout considerations power and ground recommendations when connecting power to the ad9601, it is recommended that two separate supplies be used: one for analog (avdd, 1.8 v nominal) and one for digital (drvdd, 1.8 v nominal). if only a single 1.8 v supply is available, it is routed to avdd first, then tapped off and isolated with a ferrite bead or filter choke with decoupling capacitors proceeding connection to drvdd. the user can employ several different decoupling capacitors to cover both high and low frequencies. these should be located close to the point of entry at the pc board level and close to the parts with minimal trace length. a single pc board ground plane is sufficient when using the ad9601. with proper decoupling and smart partitioning of analog, digital, and clock sections of the pc board, optimum performance is easily achieved. exposed paddle thermal heat slug recommendations it is required that the exposed paddle on the underside of the adc be connected to analog ground (agnd) to achieve the best electrical and thermal performance of the ad9601. an exposed, continuous copper plane on the pcb should mate to the ad9601 exposed paddle, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be solder-filled or plugged. to maximize the coverage and adhesion between the adc and pcb, partition the continuous plane by overlaying a silkscreen on the pcb into several uniform sections. this provides several tie points between the two during the reflow process. using one continuous plane with no partitions guarantees only one tie point between the adc and pcb. see figure 43 for a pcb layout example. for detailed information on packaging and the pcb layout of chip scale packages, see application note an-772, a design and manufacturing guide for the lead frame chip scale package . silkscreen partition pin 1 indicator 07100-018 figure 43. typical pcb layout cml the cml pin should be decoupled to ground with a 0.1 f capacitor, as shown in figure 45 . rbias the ad9601 requires the user to place a 10 k resistor between the rbias pin and ground. this resistor sets the master current reference of the adc core and should have at least a 1% tolerance. ad9601 configuration using the spi the ad9601 spi allows the user to configure the converter for specific functions or operations through a structured register space inside the adc. this gives the user added flexibility to customize device operation depending on the application. addresses are accessed (programmed or read back) serially in one-byte words. each byte can be further divided down into fields, which are documented in the memory map section. there are three pins that define the serial port interface or spi to this particular adc. they are the spi sclk/dfs, spi sdio/dcs, and csb pins. the sclk/dfs (serial clock) is used to synchronize the read and write data presented the adc. the sdio/dcs (serial data input/output) is a dual-purpose pin that allows data to be sent and read from the internal adc memory map registers. the csb is an active low control that enables or disables the read and write cycles (see table 8 ). table 8. serial port pins mnemonic function sclk sclk (serial clock) is the serial shift clock in. sclk is used to synchronize serial interface reads and writes. sdio sdio (serial data input/ output) is a dual-purpose pin. the typical role for this pin is an input and output depending on the instruction being sent and the relative position in the timing frame. csb csb (chip select bar) is an active low control that gates the read and write cycles. reset master device reset. when asserted, device assumes default settings. active low. the falling edge of the csb, in conjunction with the rising edge of the sclk, determines the start of the framing. an example of the serial timing and its definitions can be found in figure 44 and table 10 . during an instruction phase, a 16-bit instruction is transmitted. data then follows the instruction phase and is determined by the w0 and w1 bits, which is 1 or more bytes of data. all data is composed of 8-bit words. the first bit of each individual byte of serial data indicates whether this is a read or write command. this allows the serial data input/output (sdio) pin to change direction from an input to an output. data can be sent in msb or in lsb first mode. msb first is default on power-up and can be changed by changing the configuration register. for more information about this feature and others, see interfacing to high speed adcs via spi at www.analog.com .
ad9601 rev. 0 | page 21 of 32 hardware interface the pins described in table 8 comprise the physical interface between the users programming device and the serial port of the ad9601. all serial pins are inputs, which is an open-drain output and should be tied to an external pull-up or pull-down resistor (suggested value of 10 k). this interface is flexible enough to be controlled by either proms or pic microcontrollers as well. this provides the user with an alternate method to program the adc other than a spi controller. if the user chooses not to use the spi interface, some pins serve a dual function and are associated with a specific function when strapped externally to avdd or ground during device power- on. the configuration without the spi section describes the strappable functions supported on the ad9601. configuration without the spi in applications that do not interface to the spi control registers, the spi sdio/dcs and spi sclk/dfs pins can alternately serve as standalone cmos-compatible control pins. when the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer. in this mode, the spi csb chip select should be connected to ground, which disables the serial port interface. table 9. mode selection mnemonic external voltage configuration avdd duty cycle stabilizer enabled spi sdio/dcs agnd duty cycle stabilizer disabled avdd twos complement enabled spi sclk/dfs agnd offset binary enabled don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t hi t clk t lo t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 07100-019 figure 44. serial port interface timing diagram
ad9601 rev. 0 | page 22 of 32 table 10. serial timing definitions parameter timing (minimum, ns) description t ds 5 setup time between the data and the rising edge of sclk t dh 2 hold time between the data and the rising edge of sclk t clk 40 period of the clock t s 5 setup time between csb and sclk t h 2 hold time between csb and sclk t hi 16 minimum period that sclk should be in a logic high state t lo 16 minimum period that sclk should be in a logic low state t en_sdio 1 minimum time for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure 44 ) t dis_sdio 5 minimum time for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figure 44 ) table 11. output data format input (v) condition (v) offset binary output mode d11 to d0 twos complement mode d11 to d0 gray code mode (spi accessible) d11 to d0 or vin+ ? vin? < 0.62 0000 0000 0000 0000 0000 0000 0000 0000 0000 1 vin+ ? vin? = 0.62 0000 0000 0000 0000 0000 0000 0000 0000 0000 0 vin+ ? vin? = 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0 vin+ ? vin? = 0.62 1111 1111 1111 1111 1111 1111 0000 0000 0000 0 vin+ ? vin? > 0.62 + 0.5 lsb 1111 1111 1111 1111 1111 1111 0000 0000 0000 1
ad9601 rev. 0 | page 23 of 32 memory map reading the memory map table each row in the memory map table has eight address locations. the memory map is roughly divided into three sections: chip configuration register map (address 0x00 to address 0x02), transfer register map (address 0xff), and program register map (address 0x08 to address 0x2a). the addr (hex) column of the memory map indicates the register address in hexadecimal, and the default value (hex) column shows the default hexadecimal value that is already written into the register. the bit 7 (msb) column is the start of the default hexadecimal value given. for example, hexadecimal address 0x09, clock, has a hexa decimal default value of 0x01. this means bit 7 = 0, bit 6 = 0, bit 5 = 0, bit 4 = 0, bit 3 = 0, bit 2 = 0, bit 1 = 0, and bit 0 = 1, or 0000 0001 in binary. the default value enables the duty cycle stabilizer. overwriting this default so that bit 0 = 0 disables the duty cycle stabilizer. for more information on this and other functions, consult the interfacing to high speed adcs via spi user manual at www.analog.com . reserved locations undefined memory locations should not be written to other than their default values suggested in this data sheet. addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. default values coming out of reset, critical registers are preloaded with default values. these values are indicated in table 12 . other registers do not have default values and retain the previous value when exiting reset. logic levels an explanation of various registers follows: bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. similarly, clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. table 12. memory map register addr (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments chip configuration registers 00 chip_port_config 0 lsb first soft reset 1 1 soft reset lsb first 0 0x18 the nibbles should be mirrored by the user so that lsb or msb first mode registers correctly, regardless of shift mode. 01 chip_id 8-bit chip id, bits[7:0] ad9601 = 0x36 read- only default is unique chip id, different for each device. this is a read- only register. 02 chip_grade 0 0 0 speed grade: 01 = 200 msps 10 = 250 msps x x x read- only child id used to differentiate graded devices. transfer register ff device_update 0 0 0 0 0 0 0 sw transfer 0x00 synchronously transfers data from the master shift register to the slave. adc functions 08 modes 0 0 pdwn: 0 = full (default) 1 = standby 0 0 internal power-down mode: 000 = normal (power-up, default) 001 = full power-down 010 = standby 011 = normal (power-up) note: external pdwn pin overrides this setting 0x00 determines various generic modes of chip operation.
ad9601 rev. 0 | page 24 of 32 addr (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) default notes/ comments 09 clock 0 0 0 0 0 0 0 duty cycle stabilizer: 0 = disabled 1 = enabled (default) 0x01 od test_io reset pn23 gen: 1 = on 0 = off (default) reset pn9 gen: 1 = on 0 = off (default) output test mode: 0000 = off (default) 0001 = midscale short 0010 = +fs short 0011 = ?fs short 0100 = checker board output 0101 = pn 23 sequence 0110 = pn 9 0111 = one/zero word toggle 1000 = unused 1001 = unused 1010 = unused 1011 = unused 1100 = unused (format determined by output_mode) 0x00 when set, the test data is placed on the output pins in place of normal data. of ain_config 0 0 0 0 0 analog input disable: 1 = on 0 = off (default) cml enable: 1 = on 0 = off (default) 0 0x00 14 output_mode 0 0 interleave output mode: 1 = enabled 0 = disabled (default) output enable: 0 = enable (default) 1 = disable 0 output invert: 1 = on 0 = off (default) data format select: 00 = offset binary (default) 01 = twos complement 10 = gray code 0x00 16 output_phase output clock polarity 1 = inverted 0 = normal (default) 0 0 0 0x03 17 flex_output_delay output delay enable: 0 = enable 1 = disable output clock delay: 00000 = 0.1 ns 00001 = 0.2 ns 00010 = 0.3 ns 11101 = 3.0 ns 11110 = 3.1 ns 11111 = 3.2 ns 0x00 18 flex_vref input voltage range setting: 10000 = 0.98 v 10001 =1.00 v 10010 = 1.02 v 10011 =1.04 v 11111 = 1.23 v 00000 = 1.25 v 00001 = 1.27 v 01110 = 1.48 v 01111 = 1.50 v 0x00
ad9601 rev. 0 | page 25 of 32 evaluation board adt1-1wt pri sec nc etc1-1-13 pri sec in out evq-q2 etc1-1-13 pri sec 0.1uf volt_control vclk tri_state gnd nc output a1 a10 a2 a3 a4 a5 a6 a7 a8 a9 b1 b10 b2 b3 b4 b5 b6 b7 b8 b9 c1 c10 c2 c3 c4 c5 c6 c7 c8 c9 d1 d10 d2 d3 d4 d5 d6 d7 d8 d9 gndab1 gndab10 gndab2 gndab3 gndab4 gndab5 gndab6 gndab7 gndab8 gndab9 gndcd1 gndcd10 gndcd2 gndcd3 gndcd4 gndcd5 gndcd6 gndcd7 gndcd8 gndcd9 headerm1469169_1 a1 a10 a2 a3 a4 a5 a6 a7 a8 a9 b1 b10 b2 b3 b4 b5 b6 b7 b8 b9 c1 c10 c2 c3 c4 c5 c6 c7 c8 c9 d1 d10 d2 d3 d4 d5 d6 d7 d8 d9 gndab1 gndab10 gndab2 gndab3 gndab4 gndab5 gndab6 gndab7 gndab8 gndab9 gndcd1 gndcd10 gndcd2 gndcd3 gndcd4 gndcd5 gndcd6 gndcd7 gndcd8 gndcd9 headerm1469169_1 ain ainb avdd_clk avdd_clk1 avdd_fl avdd_fl1 avdd_pipe avdd_pipe1 avdd_pipe2 avdd_pipe3 avdd_pipe4 avdd_pipe5 avdd_ref clk clkb cml d0 d0b d1 d10 d10b d11 d11b d1b d2 d2b d3 d3b d4 d4b d5b d6 d6b d7 d7b d8 d8b d9 d9b dco dcob dgnd dgnd1 dgnd2 dor dorb dvdd dvdd1 dvdd2 pad pdn rbias resetb spcsb spsclk/dfs spsdio/dcs d5 pri sec nc 50_ohms 50_ohms alternate options dnp optional encode cr2 to make layout and parasitic loading symmetrical analog input cvhd_956 crystek crystal u6 optional encode circuits d1 d1b d0 d0b dcob dco d2b d2 9 10 12 13 14 15 2 3 4 5 6 7 8 1 16 11 rn3 9 10 12 13 14 15 2 3 4 5 6 7 8 11 6 11 rn2 9 10 12 13 14 15 2 3 4 5 6 7 8 1 16 11 d9b d9 d10b d10 d11b d11 dorb d10b dorb dor d10 9 10 12 13 14 15 2 3 4 5 6 7 8 11 6 11 cmlx 1 2 34 5 6 t3 adt1-1wt 35 36 43 46 42 41 39 38 37 34 33 32 30 44 45 40 52 51 54 18 17 20 19 53 56 55 2 1 4 3 5 10 9 12 11 14 13 16 15 50 49 8 23 48 22 21 7 24 47 57 29 31 28 27 26 25 6 u4 ad9601_csp c17 dnp r9 dnp ampout- ampout+ tout toutb 0.1uf c21 gnd 00 r90 00 r89 00 r8 r1 50 d1b d1 gnd 10k r12 l8 0 l9 0 r6 36 r5 36 r7 33 dnp r4 r16 33 csb1_cha 1 10 2 3 4 5 6 7 8 9 11 20 12 13 14 15 16 17 18 19 31 40 32 33 34 35 36 37 38 39 41 50 42 43 44 45 46 47 48 49 21 30 22 23 24 25 26 27 28 29 51 60 52 53 54 55 56 57 58 59 sdo_cha sdi_cha sclk_ch a 1 10 2 3 4 5 6 7 8 9 11 20 12 13 14 15 16 17 18 19 31 40 32 33 34 35 36 37 38 39 41 50 42 43 44 45 46 47 48 49 21 30 22 23 24 25 26 27 28 29 51 60 52 53 54 55 56 57 58 59 p7 connects to j2 p17 gnd p5 p9 gnd 0.1uf c75 r17 0 dnp volt_control c74 0.1uf gnd 1 6 2 3 5 4 e20 c61 0.1uf e19 0 r87 xtalinput 50 r3 c15 r86 10k r85 10k j3 j4 j2 r13 1k r10 1k 1 3 2 cr3 1 3 2 cr2 csb gnd vspi e10 e5 e4 dnp r15 e7 e6 1 34 2 5 t6 12 sw3 c22 0.1uf c20 dnp 0.1uf c23 dnp r14 r11 1k e9 l1 10nh 0.1uf c19 0.1uf c18 e8 0.1uf c16 1 3 4 2 5 t5 1 2 34 5 6 t2 e3 e2 e1 p4 p3 p2 p1 cml gnd gnd clkct clkct gnd avdd cml cml sdio_odm sclk_dtp toutb tinb tout gnd gnd vspi gnd gnd gnd vspi gnd e33 e32 e31 csb_dut vspi csb gnd drvdd drvdd drvdd gnd gnd gnd avdd avdd avdd avdd avdd avdd avdd avdd avdd avdd avdd e18 gnd vclk gnd gnd gnd vclk xtalinput vclk gnd gnd gnd gnd gnd p16 p10 gnd gnd gnd d8b d6b d4b d2b d0b d0 d2 d4 d6 d8 d11b d9b d7b d5b d3b d3 d5 d7 d9 d11 dcob dco gnd clk clk gnd tinb cml cml gnd gnd gnd gnd gnd gnd dor d8b d8 d7b d7 d6b d6 d5 d5b d4b d4 d3b d3 p11 connects to j1 rn1 50_ohms rn4 50_ohms 07100-045 figure 45. ad9601 evaluation board schematic page 1
ad9601 rev. 0 | page 26 of 32 + + + + in out out1 adp3338 u9 gnd in out out1 adp3338 u12 gnd in out adp3338 u11 gnd in out out1 adp3338 u10 gnd + + pj-102a +5.0v 1.8v 1.8v 3.3v 1.8v 1.8v 3.3v +5v power options 12 3 p8 vin vclk vspiext1 l6 ferrite l2 ferrite vspiextx out1 vspiextx drvddx1 drvddx vspi drvdd1 l3 ferrite l5 ferrite avdd1 l4 ferrite avddx l7 ferrite vamp1 vampx 0 r88 c11 10uf avdd1 vspiext1 vamp1 drvdd1 gnd 100pf c73 0.1uf c72 0.1uf c69 vclk c54 10uf 0.1uf c65 0.1uf c68 0.1uf c59 vspi gnd 0.1uf c39 0.1uf c63 0.1uf c62 0.1uf c27 egnd drvdd gnd 3 4 2 1 3 4 2 1 3 4 2 1 3 4 2 1 0.1uf c33 0.1uf c31 c8 10uf c9 10uf gnd gnd gnd vin gnd u7 vampx c12 10uf 0.1uf c34 egnd 3 2 1 4 t1 u8 r2 499 0.1uf c32 0.1uf c30 0.1uf c29 0.1uf c28 0.1uf c26 0.1uf c25 0.1uf c24 gnd vspiextx vin vin gnd gnd gnd gnd gnd drvddx1 gnd avddx c14 10uf 0.1uf c58 0.1uf c57 0.1uf c56 gnd vamp 0.1uf c60 0.1uf c36 0.1uf c35 vspiext 0.1uf c64 0.1uf c13 0.1uf c66 0.1uf c67 gnd 0.1uf c70 0.1uf c71 gnd avdd gnd c6 1uf c5 1uf c7 1uf c10 1uf c1 1uf c3 1uf c2 1uf c4 1uf gnd gnd gnd gnd 2 1345678 p6 vamp drvdd vspiext avdd l12 ferrite l13 ferrite l14 ferrite l15 ferrite h4 mthole6 h3 mthole6 h2 mthole6 h1 mthole6 gnd gnd egnd egnd vin gnd 0 7100-046 figure 46. ad9601 evaluation board schematic page 2
ad9601 rev. 0 | page 27 of 32 adt1-1wt pri sec nc vop von vip vin vcm enb ad8352 vcc gnd gnd gnd vcc rgn rdn rgp rdp etc1-1-13 pri sec operational amplifier ad9515 logic setup gnd c37 .1uf gnd c46 .1uf 1 34 2 5 t7 00 r46 00 r41 00 r91 dnp c76 dnp l10 l11 dnp 10k r42 00 r36 9 12 67 15 4 1 3 2 8 13 5 16 14 10 11 z1 c44 dnp c45 dnp p13 smbmst p12 smbmst 1 2 34 5 6 t4 c47 .1uf 00 r47 e14 5 r45 00 r44 10k r43 c43 dnp e13 e12 dnp r40 c42 .1uf 5 r39 r38 25 c41 dnp r37 25 c40 dnp dnp r35 dnp r34 r33 49.9 00 r94 tinb1 tout2 tinb1 tinb2 toutb2 toutb2 tinb2 tout2 gnd ampout- ampout+ cml gnd gnd vamp gnd gnd vamp gnd gnd gnd vamp gnd gnd 0.1uf smbmst smbmst dnc; 27, 28 clk clkb gnd gnd_pad out0 out0b s0 s1 s10 s2 s3 s4 s5 s6 s7 s8 s9 syncb vref rset out1 out1b ad9515 ad9515(opt_clk circuit) 2 3 5 6 7 8 9 10 11 12 13 14 15 16 25 18 19 22 23 31 32 33 u1 vclk; 1, 4, 17, 20, 21, 24, 26, 29, 30 p14 p15 0.1uf c53 r62 4.12k e17 e16 r61 240 r60 240 r59 100 0.1uf c52 0.1uf c51 0.1uf c50 r58 100 r57 00 r56 00 r55 00 r54 10k r53 00 r52 00 00 r51 dnp r50 dnp r49 c49 dnp c48 50 r48 e15 gnd s9 s3 s1 s0 s8 vclk gnd gnd gnd gnd gnd gnd clk clk s10 s7 s5 s6 s4 s2 00 r84 00 r83 00 r82 00 r81 00 r80 00 r79 00 r78 00 r77 00 r76 00 r75 00 r74 00 r73 00 r72 00 r71 00 r70 00 r69 00 r68 00 r67 00 r66 00 r65 00 r64 00 r63 vclk s6 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd s10 s9 vclk s8 s7 s5 s4 s3 s2 s1 s0 vclk vclk vclk vclk vclk vclk vclk vclk vclk 07100-047 figure 47. ad9601 evaluation board schematic page 3
ad9601 rev. 0 | page 28 of 32 spi circuitry y2 y1 vcc gnd a2 a1 nc7wz16 y2 y1 vcc gnd a2 a1 nc7wz07 4 5 3 2 16 u5 4 5 3 2 16 u3 1k r27 10k r26 1k r25 1k r24 10k r19 10k r18 csb1_cha sdo_cha sdio_odm csb_du t gnd gnd sclk_dtp gnd gnd vspi vspi vspi vspiext vspiext sdi_cha sclk_cha 07100-048 figure 48. ad9601 evaluation board schematic page 4 table 13. bill of materials ty reference designator pacage description vendor part umber 1 pcb pcb, ad9230 customer evaluation board, rev. g moog ad9230revg 7 c1, c3, c4, c5, c6, c7, c10 603 capacitor, 1 f, 0603, x5r, ceramic, 6.3 v, 10% panasonic ecj-1vb0j105k 6 c8, c9, c11, c12, c14, c55 6032-28 capacitor, 10 f, tantalum, 16 v, 10% kemet t491c106k016as 1 c17 402 capacitor, 2.0 pf, 50 v, ceramic, 0402, smd murata grm1555c1h2r0gz01d 7 c27, c32, c33, c62, c63, c64, c71 402 capacitor, 0.33 f, ceramic, x5r, 10 v, 10% murata grm155r61a334ke15d 6 c28, c29, c30, c31, c65, c70 402 capacitor, 120 pf, ceramic, c0g, 25 v, 5% murata grm1555c1h121ja01j 10 c21, c22, c23, c24, c25, c26, c34, c35, c36, c39 402 capacitor, 0.1 f, ceramic, x5r, 10 v, 10% murata grm155r71c104ka88d 1 cr4 603 led green, smt, 0603, ss-type panasonic lnj314g8tra 1 cr2 mini 3p diode, 30 v, 20 ma agilent hsms2812 1 f1 1210 fuse, 6.0 v, 2.2 a trip current resettable fuse tyco/raychem nanosmdc110f-2 15 e1, e2, e3, e4, e5, e7, e8, e9, e10, e12, e13, e14, e31, e32, e33 connector, header, 0.1" samtec tsw-150-08-g-s 2 j2, j3 sma end launch connector, sma pcb coax end launch, johnson 142 johnson 142-0701-851 10 l2, l3, l4, l5, l7, l12, l13, l14, l15, r88 1206 ferrite bead, blm, 3 a, 50 @ 100 mhz murata blm31pg500sn1l 1 p8 power jack, male, 2.1 mm power jack dc cui inc cp-102a-nd 1 r1 201 resistor, 100 , 0201, 1/20 w, 1% nic components nrc02f1000trf 1 r2 603 resistor, 499 , 0603, 1/10 w, 1% nic components nrc06f4990trf
ad9601 rev. 0 | page 29 of 32 qty reference designator package description vendor part number 2 r5, r6 402 resistor, 36 , 0402, 1/16 w, 1% panasonic erj-2gej360x 2 r7, r16 402 resistor, 15 , 0402, 1/16 w, 5% panasonic erj-2rkf15r0x 6 r10, r11, r13, r24, r25, r27 402 resistor, 1 k, 0402, 1/16 w, 1% nic components nrc04f1001trf 4 r12, r18, r19, r26, 402 resistor, 10 k, 0402, 1/16 w, 5% nic components nrc04j103trf 7 r15, c16, c18, c19, c20, r89, r90 402 resistor, 0 , 0402, 1/16 w, 5% nic components nrc04zotrf 4 rn1, rn2, rn3, rn4 0402x8 resistor array, smt 0402; 0 , ? w, 5%, resnexb-2hv panasonic exb2hv050jv 3 l1, l8, l9 603 resistor, 0 , 0603, 1/10 w, 5% nic components nrc06zotrf 1 p9, p10 805 resistor, 0 , 0805, 1/8 w, 1% nic components nrc10zotrf 1 sw3 evq- q2f03w switch, light touch smd panasonic p12937sct-nd 1 t1 2020 ferrite bead, 5 a, 50 v, 190 @ 100 mhz murata dlw5bsn191sq2l 2 t2,t3 cd542 transformer, 0.5 w, 30 ma mini-circuits adt1-1wt+ 1 u3 6-sc70 ic, buffer, inverter, uhs dual sc70-6 fairchild nc7wz16p6x 1 u5 6-sc70 ic, buffer, inverter, uhs dual od out sc70-6 fairchild nc7wz07p6x 1 u7 do-214aa diode, 50 v, 2 a micro commercial s2a-tpmstr-nd 1 u8 do-214ab diode, 30 v, 3 a (smc) micro commercial sk33-tpmsct-nd 1 u11 sot-223 voltage regulator, 3.3 v, 1.5 a analog devices adp3339akcz-3.3 2 u9, u12 sot-223 voltage regulator, 1.8 v, 1.5 a analog devices adp3339akcz-1.8 1 u4 lfcsp56 ad9230 12-bit, 170 msps/210 msps/250 msps, 1.8 v adc, lfcsp-56 analog devices ad9230bcpz-xxx 2 p7, p11 hm-zd pcb connector, 2-pr, 10-column, high speed, hm-zd, pcb-mounted tyco 6469169-1 do not install the following: 0 c2, c54 tajd capacitor, tantalum, smt 6032, 10 f, 16 v, 10% kemet t491c106k016as 0 c15, c37, c38, c40, c41, c61, c42, c43, c44, c45, c46, c47, c48, c49, c50, c51, c52, c53, c39, c56, c57, c58, c59, c74, c75, c60, c66, c67, c68, c69, c72 402 capacitor, 0.1 f, ceramic, 10% murata grm155r71c104ka88d 0 cr1 led_ss led green, uss type 0603 panasonic lnj314g8tra 0 cr3 diode schottky diode agilent hsms2812 0 805 tyco/raychem nanosmdc110f-2 0 e6, e15, e16, e17, e18, e19, e20 connector, header, 0.1" samtec tsw-150-08-g-s 0 j1 10-pin header tsw-110-08-g-d samtec tsw-110-08-g-d 0 j4 sma connector, pcb coax sma end launch, johnson 142 johnson 142-0701-851 0 l6 1206 inductor, 10 nh murata blm31p500s 0 p12, p13, p14, p15 sma amphenol rf arfx1231-nd
ad9601 rev. 0 | page 30 of 32 qty reference designator package description vendor part number 0 r3, r14, r33, r34, r35, r48, r49 402 resistor, 49.9 susumu rr0510r-49r9-d 0 r42, r43, r54, r85, r86 402 resistor, 10 k nic components nrc04j103trf 0 r28, r29, r30, r31, r32 402 resistor, 5 k nic components nrc04f4991trf 0 r37, r38 402 resistor, 25 nic components nrc04f24r9trf 0 r39, r45 402 resistor, 5 nic components nrc04j5r1trf 0 r58, r59 402 resistor, 100 nic components nrc04f1000trf 0 r60, r61 402 resistor, 240 nic components nrc04j241trf 0 r8, r9, r17, r36, r40, r41, r44, r46, r47, r87, r50, r51, r52, r53, r55, r56, r57, r62, r63, r64, r65, r66, r67, r68, r69, r70, r71, r72, r73, r74, r75, r76, r77, r78, r79, r80, r81, r82, r83, r84 402 resistor, 0 nic components nrc04zotrf 0 p1, p2, p16, p17 805 resistor, 0 nic components nrc10zotrf 0 sw1 evq- q2f03w switch, light touch smd panasonic p12937sct-nd 0 t4 transformer, rf, 0.4 mhz to 800 mhz, smd case style cd542 mini-circuits adt1-1wt+ 0 t5, t6 sm-22 balun m/a-com maba007159-0000 0 u2 soic-8 pic12f629 microchip tech pic12f629-i/sn 0 u6 crystal cvhd_956 crystal cvhd_956 0 u10 sot-223 regulator adp3339akcz-5.0 0 z1 16csp4x4 ad8352 0 u1 16csp8x8 ad9515 0 p6 8-pin power connector post wieland z5.530.0825.0 0 p6 8-pin power connector top wieland 25.602.2853.0
ad9601 rev. 0 | page 31 of 32 outline dimensions compliant to jedec standards mo-220-vlld-2 112805-0 pin 1 indicator top view 7.75 bsc sq 8.00 bsc sq 1 56 14 15 43 42 28 29 4.45 4.30 sq 4.15 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0 .85 0 .80 6.50 ref seating plane 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 0.05 max 0.02 nom 0.30 min exposed pad (bottom view) figure 49. 56-lead lead frame chip scale package [lfcsp_vq] 8 mm 8 mm body, very thin quad (cp-56-2) dimensions shown in millimeters ordering guide model temperature range package description package option ad9601bcpz-200 1 ?40c to +85c 56-lead lead frame chip scale package [lfcsp_vq] cp-56-2 ad9601bcpz-250 1 ?40c to +85c 56-lead lead frame chip scale package [lfcsp_vq] cp-56-2 AD9601-250EBZ 1 cmos evaluation board with ad9601bcpz-250 1 z = rohs compliant part.
ad9601 rev. 0 | page 32 of 32 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07100-0-11/07(0)

▲Up To Search▲

Price & Availability of AD9601-250EBZ

	To Download AD9601-250EBZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .